Guides
Evergreen explainers and how-to guides from The Silicon Ledger: background that stays useful beyond the news cycle.
Evergreen explainers and how-to guides from The Silicon Ledger: background that stays useful beyond the news cycle.
- HBM4 vs HBM3E: What Changed in High-Bandwidth Memory HBM4 doubles the interface to 2,048 bits per stack. How it compares with HBM3E on speed, bandwidth, capacity and power, and which chips use it in 2026.
- What Is CoWoS? TSMC's CoWoS-S, CoWoS-R and CoWoS-L Explained CoWoS is TSMC's 2.5D packaging for AI chips with HBM. How CoWoS-S, CoWoS-R and CoWoS-L differ, how large packages get, and TSMC's plans to 2029.
- PCIe Generations Explained: Speeds From PCIe 1.0 to PCIe 8.0 Each PCIe generation roughly doubles lane bandwidth. Transfer rates, real x16 bandwidth, encoding changes and the status of PCIe 7.0 and 8.0 in 2026.
- High-NA EUV vs EUV: What 0.55 NA Lithography Changes High-NA EUV raises numerical aperture from 0.33 to 0.55 for 8 nm resolution. How it differs from standard EUV, its trade-offs and who uses it in 2026.