PCIe Generations Explained: Speeds From PCIe 1.0 to PCIe 8.0

Each PCI Express generation roughly doubles the bandwidth of a lane. The raw rate went from 2.5 GT/s for PCIe 1.0 to 5, 8, 16, 32 and 64 GT/s, and to 128 GT/s for PCIe 7.0, with PCIe 8.0 targeting 256 GT/s. PCIe 3.0 is the exception in the sequence: it combined a smaller rate increase with more efficient encoding to double usable throughput. In a x16 slot, usable bandwidth runs from about 4 GB/s in each direction for PCIe 1.0 to about 242 GB/s in each direction for PCIe 7.0.

As of October 2026, PCIe 7.0 is the newest finished specification, released on June 11, 2025. PCIe 8.0 is at draft 0.5, and PCI-SIG, the group that writes the standard, plans to release it by 2028. Below are the numbers for every generation and what changed along the way.

GT/s vs GB/s: how to read PCIe speeds

PCI-SIG quotes speeds in gigatransfers per second (GT/s), the raw rate at which bits cross one lane in one direction. Usable throughput is lower because part of the raw rate goes to line encoding:

• PCIe 1.0 and 2.0 use 8b/10b encoding, so 20% of the raw rate is overhead.
• PCIe 3.0, 4.0 and 5.0 use 128b/130b encoding, with overhead of about 1.5%.
• PCIe 6.0 and later send data in fixed 256-byte units called FLITs, of which 242 bytes carry packet data and the remaining 14 hold 8 bytes of error checking (CRC) and 6 bytes of forward error correction (FEC).

Each lane is a pair of one-way links, so traffic flows in both directions at once. PCI-SIG's headline figures, such as 512 GB/s for a PCIe 7.0 x16 link, count both directions together. The per-direction numbers in this guide show what one device can send or receive at a time.

PCIe speeds by generation

The list shows the year each final specification was released, the rate per lane and the usable bandwidth of a x16 link in one direction, rounded and after encoding overhead (overview):

• PCIe 1.0 (2003): 2.5 GT/s, 8b/10b, about 4 GB/s at x16 (250 MB/s per lane).
• PCIe 2.0 (2007): 5 GT/s, 8b/10b, about 8 GB/s.
• PCIe 3.0 (2010): 8 GT/s, 128b/130b, about 15.8 GB/s.
• PCIe 4.0 (2017): 16 GT/s, 128b/130b, about 31.5 GB/s.
• PCIe 5.0 (2019): 32 GT/s, 128b/130b, about 63 GB/s.
• PCIe 6.0 (2022): 64 GT/s, PAM4 signaling with FLIT encoding, about 121 GB/s.
• PCIe 7.0 (2025): 128 GT/s, PAM4 with FLIT encoding, about 242 GB/s.
• PCIe 8.0 (planned by 2028): 256 GT/s, with PCI-SIG targeting up to 1.0 TB/s over x16 counting both directions.

Narrower links scale in proportion. A x4 NVMe SSD gets a quarter of the x16 figure: about 7.9 GB/s per direction on PCIe 4.0 and about 15.8 GB/s on PCIe 5.0.

What changed in PCIe 6.0

Up to PCIe 5.0, every generation used the same two-level (NRZ) signal and gained speed by running it faster; PCIe 3.0 also moved to more efficient encoding. PCIe 6.0 switched to PAM4, which uses four voltage levels to carry two bits per symbol, so the data rate doubled without doubling the signaling frequency (PCI-SIG). PAM4 is more prone to bit errors, so PCIe 6.0 added lightweight FEC and CRC, organised in FLITs. PCI-SIG lists up to 256 GB/s over x16, a figure that combines both directions, and backward compatibility with all earlier generations.

The final PCIe 6.0 specification was published in January 2022, but volume products took years. In March 2026 Micron said its 9650, a data-center drive rated at up to 28 GB/s for sequential reads, was the first PCIe Gen6 SSD in high-volume production (Micron).

PCIe 7.0: finished, aimed at data centers

PCI-SIG released the PCIe 7.0 specification to its members on June 11, 2025. It keeps PAM4 signaling and FLIT encoding, doubles the rate to 128 GT/s, delivers up to 512 GB/s over x16 in both directions combined and stays backward compatible (PCI-SIG announcement).

PCI-SIG names AI and machine learning, 800G Ethernet, cloud, hyperscale data centers, high-performance computing and quantum computing as target markets. Its feature goals for 7.0 also include optical links between PCIe 6.4- and 7.0-compliant devices, for longer reach across racks and pods (PCI-SIG).

PCIe 8.0: 256 GT/s, due by 2028

PCI-SIG announced PCIe 8.0 in August 2025. Version 0.3 reached members in September 2025, and draft 0.5, the official first draft, followed on May 1, 2026, which PCI-SIG described as ahead of the usual schedule (PCI-SIG blog). The stated objectives are:

• 256 GT/s per lane and up to 1.0 TB/s bidirectionally over x16;
• evaluating new connector technology;
• meeting latency, FEC and reliability targets;
• backward compatibility with earlier generations;
• protocol changes to improve bandwidth, and further techniques to reduce power.

How a PCIe specification is developed

PCI-SIG drafts move through fixed checkpoints: version 0.3 (concept), 0.5 (first draft with the complete architecture), 0.7 (complete draft, with electrical specifications validated on test silicon), 0.9 (final draft for intellectual-property review) and 1.0 (final release). PCIe 7.0 went from draft 0.5 in April 2024 to the final release in June 2025. Products follow the final specification by years, as PCIe 6.0 showed.

Backward compatibility and lane counts

Every generation keeps backward compatibility, so a PCIe 5.0 SSD works in a PCIe 4.0 slot and a PCIe 4.0 card works in a PCIe 5.0 slot. The link runs at the highest speed both ends support.

Lane count matters as much as generation. A PCIe 4.0 x16 link and a PCIe 5.0 x8 link offer about the same bandwidth, roughly 31.5 GB/s per direction, which is why platform makers can split newer lanes between more devices. For the chips and platforms that implement these links, see our Chips section and wider Industry coverage.

How to check the PCIe link of a device

On Linux, running sudo lspci -vv prints two lines for each PCIe device that answer the question directly. LnkCap shows the highest speed and width the device supports, and LnkSta shows what the link actually negotiated. Speeds appear as transfer rates, so 16GT/s means PCIe 4.0 and 32GT/s means PCIe 5.0.

If LnkSta reports a lower speed or fewer lanes than LnkCap, the device has trained below its maximum. Common causes are a slot wired with fewer lanes than its physical length suggests, a slot that shares lanes with another device, or power management lowering the link speed while the device is idle. Developers who benchmark storage or accelerators should check this before comparing results; more tooling news is in our Developers section.

Frequently asked questions

How fast is PCIe 5.0 compared with PCIe 4.0?

PCIe 5.0 runs at 32 GT/s per lane, twice PCIe 4.0's 16 GT/s. A x4 SSD link offers about 15.8 GB/s per direction on PCIe 5.0 against about 7.9 GB/s on PCIe 4.0.

Is PCIe 7.0 available?

The PCIe 7.0 specification has been final since June 11, 2025. PCI-SIG targets data-center uses such as AI and 800G Ethernet first, and products usually arrive years after a specification is released.

When will PCIe 8.0 be released?

PCI-SIG plans to release the full PCIe 8.0 specification to members by 2028. Draft 0.5 was published on May 1, 2026.

Are PCIe generations backward compatible?

Yes. A PCIe device works in a slot of an older or newer generation, as long as it physically fits, and the link runs at the highest speed both sides support.

What does GT/s mean in PCIe?

GT/s stands for gigatransfers per second, the raw number of bits sent per second on one lane in one direction, before encoding overhead is subtracted.