TSMC Process Nodes Explained: N3, N2, N2P, A16 and A14

TSMC's leading-edge roadmap runs from N3, its last FinFET node, to N2, its first node with nanosheet (gate-all-around) transistors. N2 entered volume production in the fourth quarter of 2025, and TSMC says it offers 10–15% more speed or 25–30% lower power than N3E, plus more than 15% higher chip density. A16 adds backside power delivery to the N2 family and is scheduled for the second half of 2026, while A14 is the next full node, due for volume production in 2028. Below is what each name covers, when it ships and the gains TSMC itself claims, as of October 2026.

The roadmap at a glance

N3 family (FinFET): N3 in volume production since late 2022, followed by N3E, N3P, N3X and the automotive N3A.
N2 family (first-generation nanosheet): N2 since 4Q 2025, N2P scheduled for the second half of 2026, N2U planned for 2028.
A16 (nanosheet plus Super Power Rail): scheduled for the second half of 2026 and aimed at high-performance computing chips.
A14 family (second-generation nanosheet): A14 risk production in 2027 and volume production in 2028, then A13 and A12 in 2029.

Every percentage on this page is a TSMC projection measured against a baseline TSMC picked. The figures describe the manufacturing process, not any finished chip, and because each step uses a different reference node they should be read one comparison at a time.

What "3nm" and "2nm" actually mean

Node names stopped matching a physical dimension long ago. As IEEE Spectrum pointed out in 2020, most key dimensions of a "7nm" transistor are well above 7 nm, and the mismatch goes back about two decades. N3 and N2 are generation labels: each marks a package of density, speed and power gains over the one before.

The A in A16 and A14 works the same way. TSMC's releases do not attach a nanometre figure to these names; the letter is usually read as angstrom (0.1 nm), which is why A16 and A14 are often called 1.6nm-class and 1.4nm-class nodes. Names from different foundries are not directly comparable either, so density and power data say more than the label.

N3: TSMC's last FinFET generation

TSMC held its 3nm volume production ceremony in December 2022. Against N5, it claimed up to 1.6 times the logic density and 30–35% lower power at the same speed. N3 is the last TSMC node built on FinFETs, where the gate wraps a vertical silicon fin on three sides.

The family grew through variants that TSMC set out at its 2023 Technology Symposium:

N3E: the enhanced 3nm baseline, due in 2023, and the reference point for N2's claims.
N3P: about 5% more speed at the same leakage, 5–10% lower power at the same speed and 1.04 times the chip density of N3E, with production then planned for the second half of 2024.
N3X: a high-performance option about 5% faster than N3P at a 1.2V drive voltage, with N3P's density, then planned for volume production in 2025.
N3AE and N3A: automotive versions. N3AE gave car-chip designers early design kits from 2023, and TSMC says N3A enters production in 2026.

3nm is still a bigger business than 2nm. In the second quarter of 2026 it produced 30% of TSMC's wafer revenue against 3% for 2nm, according to TSMC's second-quarter results. On its July 2026 earnings call, TSMC said it is adding three more 3nm fabs, in Taiwan, Arizona and Japan.

N2: the switch to nanosheet transistors

N2 is TSMC's first node with nanosheet transistors, a gate-all-around design in which the gate surrounds a stack of thin horizontal silicon sheets. Enclosing the channel on all sides gives the gate tighter control over leakage than a fin allows.

According to TSMC's 2nm technology page, N2 entered volume production in 4Q 2025, and Fab 20 and Fab 22 are its 2nm production sites, in Hsinchu and Kaohsiung. On its January 2025 earnings call, TSMC put N2's gains over N3E at 10–15% more speed at the same power, 25–30% lower power at the same speed and more than 15% higher chip density. N2 also brought NanoFlex, which lets designers mix short, area-efficient standard cells with taller, faster ones on the same chip. For the third quarter of 2026, TSMC said it expected a steep ramp of 2nm.

N2P and N2U

N2P extends N2 with further performance and power gains on the same transistor technology and is meant for both smartphone and HPC chips. As of October 2026, TSMC's 2nm page lists it for volume production in the second half of 2026.

N2U, announced at the April 2026 symposium, uses design-technology co-optimisation to add 3–4% speed or 8–10% lower power over N2P, with 1.02–1.03 times the logic density. It is planned for production in 2028. The same announcement covered N2A, TSMC's first automotive nanosheet process, which TSMC expects to complete AEC-Q100 qualification in 2028.

A16: N2-class transistors with backside power

A16 pairs nanosheet transistors with Super Power Rail (SPR), TSMC's backside power delivery scheme. In a conventional chip, power lines and signal wires share the stack of metal layers built above the transistors. SPR relocates the power network to the underside of the wafer and leaves the front-side wiring for signals only, which TSMC says raises logic density and performance.

TSMC introduced A16 in April 2024. Compared with N2P, it claims:

8–10% more speed at the same voltage
15–20% lower power at the same speed
7–10% higher chip density, with the top of that range quoted for data centre products

TSMC targets A16 at specific high-performance computing designs where signal routing is crowded and power delivery is dense. On its January 2026 earnings call, it said A16 volume production was on track for the second half of 2026, and it groups A16 with N2 and N2P as part of the N2 family rather than treating it as a new full node.

A14: the next full node

TSMC unveiled A14 in April 2025 as the full-node successor to N2. It uses TSMC's second generation of nanosheet transistors and moves the cell architecture from NanoFlex to NanoFlex Pro. At launch, TSMC claimed that against N2 it would deliver up to 15% more speed at the same power, up to 30% lower power at the same speed and more than 20% higher logic density. In its 2026 earnings calls it has quoted 10–15% speed, 25–30% power and close to 20% chip density; logic-only density and whole-chip density are measured differently, so the two sets of numbers sit side by side.

On the July 2026 call, TSMC said A14 risk production starts in 2027 and volume production follows in 2028. Two derivatives announced in April 2026 extend the family, and one of them brings backside power to it:

A13: a direct optical shrink of A14 that saves about 6% of die area, keeps design rules backward compatible with A14 and is due in 2029.
A12: the A14 platform with TSMC's Super Power Rail backside power delivery, aimed at AI and HPC, also due in 2029.

A16 vs A14: which is more advanced?

A14 is the newer generation. A16 arrives first, in the second half of 2026, and improves on N2P mainly by moving power delivery to the back of the wafer while keeping first-generation nanosheet transistors. A14, due in 2028, shrinks the transistors themselves with second-generation nanosheets, and its backside power version is A12 in 2029.

The intended markets also differ. TSMC pitches A16 at specific HPC designs, while it describes customer interest in A14 from both smartphone and HPC/AI applications.

How to read TSMC's node claims

Speed or power, not both. Each speed gain is quoted at equal power and each power cut at equal speed; a real design trades between them.
Logic density versus chip density. Logic density counts logic cells only. Chip density reflects a whole die that also holds SRAM and analog circuits, which tend to shrink less.
Baselines shift. N2 is compared with N3E, A16 and N2U with N2P, A14 with N2, and A13 with A14.
Schedules move. TSMC updates its roadmap each April at its North America Technology Symposium and gives status updates on quarterly earnings calls.

The packaging that turns these dies into AI accelerators is covered in our CoWoS explainer, and the lithography machines behind future shrinks in High-NA EUV vs EUV. Ongoing foundry news sits in our Chips section, part of Industry coverage.

Frequently asked questions

Is TSMC 2nm in mass production?

Yes. TSMC says N2 entered volume production in the fourth quarter of 2025 at its Hsinchu and Kaohsiung sites, and 2nm made up 3% of its wafer revenue in the second quarter of 2026.

What is the difference between TSMC N2 and N2P?

N2P is an enhanced version of N2 that adds performance and power gains on the same nanosheet technology. As of October 2026, TSMC lists it for volume production in the second half of 2026.

Does TSMC N2 use backside power delivery?

No. N2 and N2P deliver power from the front of the wafer; TSMC's first node with backside power is A16, which uses Super Power Rail, and A12 brings the same approach to the A14 platform in 2029.

When will TSMC A14 be available?

TSMC plans A14 risk production in 2027 and volume production in 2028. When chips built on it reach products depends on each customer's own schedule.

What does the A in TSMC A16 stand for?

TSMC does not define it in its releases, but it is generally read as angstrom, a tenth of a nanometre, which makes A16 a 1.6nm-class name. Like N3 and N2, it is a generation label, not a measured feature size.