Backside Power Delivery Explained: Intel PowerVia vs TSMC Super Power Rail

Backside power delivery (BSPDN) moves a chip's power wiring from above the transistors to the underside of the wafer, so the top metal layers carry only signals. Intel calls its version PowerVia and builds it into the 18A process. TSMC calls its version Super Power Rail and plans it for A16, a node TSMC's roadmap places in production in the second half of 2026.

The idea is simple. The execution is not, because it needs a thinned wafer, a bonded carrier and new design and debug methods. This page explains what moves, why it helps, how the two approaches differ and what it costs. Intel's 18A is already in shipping laptop chips, while TSMC's A16 had not been confirmed as shipping when this page was checked in late October 2026.

What backside power delivery changes

In a conventional chip, transistors sit at the bottom and a stack of metal layers is built on top. Those layers carry both signals and power, and they compete for the same space. Power has to travel down through many thin, resistive layers to reach the transistors.

With backside power, the wafer is flipped and thinned after the transistors and signal wiring are built. A separate power network is then built on the exposed back side. The general description is the same for every vendor: signals on the front, power on the back.

Why chipmakers want it

• Less IR drop. IR drop is the voltage lost as current crosses resistive wiring. A shorter, wider power path loses less, so transistors see a steadier supply.
• Less routing congestion. Moving power lines off the front frees room for signal wires.
• More density. Standard cells can sit closer together when the front side does not have to make room for power rails.

These gains matter most for large, power-hungry processors such as server CPUs and AI accelerators, where supply noise and wire congestion limit clock speed.

Intel PowerVia on 18A

PowerVia ships with Intel's 18A node, which pairs it with RibbonFET, Intel's gate-all-around transistor (see our explainer on GAAFET vs FinFET). The first client family on 18A, Panther Lake, launched at CES in January 2026 as Core Ultra series 3, according to the Panther Lake reference entry.

In PowerVia, transistors are built on the front of the wafer first. Narrow vias are etched through the silicon, a carrier wafer is bonded on top, the stack is flipped, and the original wafer is polished until the via ends are exposed. The backside power network is built on that surface. IEEE Spectrum describes this sequence in detail.

Intel's published results came from a test chip on its older Intel 4 process, not from 18A products. As IEEE Spectrum reported, Intel measured a frequency gain of more than 6 percent and about 30 percent less power loss, with cells packed up to 95 percent full in some areas. Treat these as Intel's test-chip figures, not as measured gains in shipping processors.

TSMC Super Power Rail on A16

TSMC introduced A16 at its North American Technology Symposium in April 2024. A16 combines nanosheet transistors with Super Power Rail. TSMC compared A16 with N2P and claimed:

• 8 to 10 percent higher speed at the same supply voltage, or
• 15 to 20 percent lower power at the same speed, and
• up to 1.10 times the chip density for data-centre products.

TSMC says the design suits high-performance computing chips with complex signal routing and dense power networks. TSMC's 2024 announcement said only that A16 is planned for 2026, and later roadmap summaries put production in the second half of that year. Check TSMC's latest quarterly statement for whether volume production has started. Our guide to TSMC process nodes N3, N2, A16 and A14 places A16 in the wider roadmap.

TSMC first planned backside power for N2P, then dropped it from that node, according to AnandTech's April 2024 report. A16 is where TSMC's backside power arrives.

PowerVia vs Super Power Rail

Both move power to the back. The difference is how the back-side wires reach the transistors.

• PowerVia: backside power connects to the transistor layer through vias that pass through the thinned silicon.
• Super Power Rail: as TrendForce summarised in 2024, the power lines connect directly to the transistor's source and drain.

TSMC has not published full process details, so any comparison between the two beyond these claims and the vendors' own numbers is speculation. The two sets of figures also use different baselines: Intel's came from an Intel 4 test chip, TSMC's compare A16 with N2P.

Samsung and imec

Samsung's first backside-power node, SF2Z, is listed for volume production in 2027, according to Wikipedia's 2 nm process table. The research institute imec has worked on backside power as a way to relieve congestion. Its Eric Beyne says it could also allow more backside decoupling and more power domains, as quoted by Semiconductor Engineering.

The trade-offs

• Heat. Silicon used to act as a radiator. With a thinned die and denser cells, heat has less silicon to spread through. Semiconductor Engineering reports that engineers at Ansys and Intel flag this as a design concern, and that designers need thermal-aware place-and-route.
• Manufacturing. Wafer thinning, bonding and flipping add steps and cost, and the two sides of the wafer have to line up precisely.
• Debug. Finding defects is harder when transistors sit between two wiring stacks. Intel has said PowerVia chips can still be tested, but independent data on debug effort in volume production is scarce.
• Design tools. Chip designers need new rules and tools to plan power on one side and signals on the other.

Packaging is the other half of the story for big chips. See our explainer on CoWoS packaging, and for more on fab technology browse our Chips coverage.

Frequently asked questions

What is backside power delivery?

It is a chip manufacturing technique that places the power-supply wiring on the back of the wafer instead of above the transistors. Signal wiring stays on the front, which reduces voltage loss and congestion.

What is PowerVia?

PowerVia is Intel's backside power delivery technology, used in its 18A process. It connects back-side power wiring to the transistors through vias that pass through the thinned silicon.

What is TSMC's Super Power Rail?

Super Power Rail is TSMC's backside power design for its A16 node. It connects power lines directly to the transistor source and drain, and TSMC's roadmap places A16 in production in the second half of 2026.

Does backside power make chips run hotter?

It can concentrate heat, because cells are packed more tightly and the die is thinner. Engineers address this with thermal-aware layout and by using copper wiring to carry heat away.