HBM4 vs HBM3E: What Changed in High-Bandwidth Memory

HBM4 differs from HBM3E mainly in width: each HBM4 stack talks to the processor over a 2,048-bit interface, twice the 1,024 bits of HBM3E. The JEDEC standard sets HBM4 at up to 8 Gb/s per pin and up to 2 TB/s per stack, against roughly 1.2 TB/s for a fast HBM3E stack, and allows stacks of up to 16 dies and 64 GB.

Shipping parts already run well above the standard. As of October 2026, Samsung quotes 11.7 Gb/s and up to 3.3 TB/s per HBM4 stack, and Micron more than 11 Gb/s and more than 2.8 TB/s. This guide compares the two generations, explains what changed and lists the chips that use HBM4.

What HBM is

High-bandwidth memory is DRAM built as a vertical stack. Several memory dies sit on top of a base die and are linked by through-silicon vias, and the finished stack is placed right beside the processor inside the same package.

The design trades speed per pin for width. DDR5 and GDDR7 chips move data over relatively narrow interfaces at high speed per pin; an HBM stack uses a very wide interface at a moderate speed per pin. That short, wide connection gives AI accelerators the bandwidth they need, but it also requires advanced packaging, such as TSMC's CoWoS, to route thousands of wires between the processor and each stack.

HBM3E in brief

HBM3E is the faster extension of HBM3, the generation JEDEC standardised in January 2022 with a 1,024-bit interface and 16 channels per stack (overview). Memory makers announced HBM3E in 2023 and began mass production in 2024.

Micron's HBM3E product page lists pin speeds above 9.2 Gb/s, more than 1.2 TB/s per stack, 16 channels with 32 pseudo-channels, 24 GB in an 8-high stack and 36 GB in a 12-high stack. Samsung's HBM4 announcement puts the top HBM3E pin speed at 9.6 Gb/s. Nvidia's Blackwell generation, announced in March 2024, uses HBM3E.

What the HBM4 standard changes

JEDEC published HBM4 as JESD270-4 on April 16, 2025. The main changes:

• Interface: 2,048 bits per stack, up from 1,024.
• Speed and bandwidth: up to 8 Gb/s per pin and up to 2 TB/s per stack in the base specification.
• Channels: 32 independent channels per stack, each with two pseudo-channels, versus 16 channels in HBM3.
• Capacity: 4-high, 8-high, 12-high and 16-high stacks built from 24 Gb or 32 Gb dies, up to 64 GB per stack. The HBM3 standard already provided for 64 GB stacks on paper, so the ceiling itself is not new.
• Power: vendor-specific I/O voltages (VDDQ) of 0.7, 0.75, 0.8 or 0.9 V and core voltages (VDDC) of 1.0 or 1.05 V.
• Reliability: Directed Refresh Management (DRFM) for better row-hammer mitigation.
• Compatibility: HBM4 stays compatible with existing HBM3 controllers, so one controller design can drive either memory type.

The doubled width does most of the work. HBM4 reaches 2 TB/s at 8 Gb/s, a lower pin speed than HBM3E, because twice as many data lines carry traffic at once: 2,048 lines at 8 Gb/s equal about 2,048 GB/s. The price is twice as many connections per stack, which puts more load on the package and the interposer underneath.

A logic base die from a foundry

The bottom die of each stack handles the interface to the processor, and with HBM4 it moves to logic manufacturing processes. TSMC offers N12 and N3 logic base dies for HBM4 (TSMC, April 2025), and Samsung builds its base die on its own 4 nm foundry process. A logic base die also opens the door to custom HBM designed for a specific customer; Samsung says custom HBM samples will follow in 2027.

HBM4 vs HBM3E at a glance

• Interface width per stack: 1,024 bits for HBM3E; 2,048 bits for HBM4.
• Channels per stack: 16 for HBM3E; 32 (64 pseudo-channels) for HBM4.
• Pin speed: about 9.2 to 9.6 Gb/s for HBM3E products; 8 Gb/s in the HBM4 standard and more than 11 Gb/s in HBM4 now shipping from Micron and Samsung (Samsung quotes 11.7 Gb/s).
• Bandwidth per stack: about 1.2 TB/s for HBM3E; 2 TB/s in the HBM4 standard; more than 2.8 TB/s (Micron) and up to 3.3 TB/s (Samsung) in shipping parts.
• Capacity per stack: 24 GB (8-high) or 36 GB (12-high) in Micron's HBM3E line-up; up to 64 GB allowed for HBM4, with 36 GB 12-high and 48 GB 16-high parts announced.
• Power efficiency: Samsung claims a 40% improvement for its HBM4 over HBM3E; Micron claims more than 20% for its 36 GB part.

Who makes HBM4, as of October 2026

• SK hynix said on September 12, 2025 that it had completed HBM4 development and readied mass production, with 2,048 I/O terminals, speeds above 10 Gb/s and power efficiency more than 40% better than its previous generation.
• Samsung announced mass production and commercial shipments on February 12, 2026: 11.7 Gb/s with headroom to 13 Gb/s, up to 3.3 TB/s per stack, 24 GB to 36 GB in 12-high stacks and a planned 48 GB 16-high version, built on its sixth-generation 10 nm-class (1c) DRAM process.
• Micron said in March 2026 that it began volume shipments of a 36 GB 12-high HBM4 stack in the first quarter of 2026, at more than 11 Gb/s and more than 2.8 TB/s, and that it has shipped 48 GB 16-high samples to customers.

Which chips use HBM4

Nvidia's Rubin GPU carries up to 288 GB of HBM4 in 12-high stacks with up to 22 TB/s of bandwidth, which Nvidia puts at 2.8 times Blackwell (Nvidia). AMD lists 432 GB of HBM4 in 12 stacks and 23.3 TB/s of peak bandwidth for its Instinct MI455X (AMD), and says the capacity is meant to keep larger models, KV caches and activations in local memory.

For more on the accelerators themselves, see our Chips coverage; supplier deals and capacity plans are tracked under Big Tech.

What comes next: HBM4E

HBM4E is the next step. In a release dated June 1, 2026, Samsung said it had begun shipping HBM4E samples, quoting 14 Gb/s per pin with headroom to 16 Gb/s, up to 3.6 TB/s per stack and 48 GB in a 12-high stack, with 32 GB (8-high) and 64 GB (16-high) versions planned (Samsung). Samsung ties the start of mass production to customer schedules.

HBM vs GDDR7 and DDR5

HBM is not a replacement for the memory in a PC. GDDR7 graphics memory and DDR5 system memory come as separate chips or modules on the circuit board, each with a far narrower interface than an HBM stack. HBM sits inside the processor package and is used where bandwidth per package matters most: data-center accelerators and similar high-end compute chips. Broader industry news on memory supply is collected in our Industry section.

Frequently asked questions

What is the difference between HBM4 and HBM3E?

HBM4 doubles the interface to 2,048 bits and the channel count to 32 per stack. The JEDEC standard allows up to 2 TB/s and 64 GB per stack, compared with about 1.2 TB/s and typically 24 GB to 36 GB for HBM3E stacks.

Is HBM4 faster than HBM3E?

Yes, per stack. The standard's 8 Gb/s pin speed is lower than HBM3E's, but the doubled width more than compensates. HBM4 shipping from Micron and Samsung runs at more than 11 Gb/s, giving roughly 2.8 to 3.3 TB/s per stack.

When did HBM4 enter mass production?

SK hynix said it was ready for mass production in September 2025. Samsung announced mass production and shipments in February 2026, and Micron began volume shipments in the first quarter of 2026.

What is HBM4E?

HBM4E is the generation after HBM4. Samsung said in mid-2026 that it had begun sampling it at 14 Gb/s per pin and up to 3.6 TB/s per stack.

Which GPUs use HBM4?

Nvidia's Rubin GPU uses up to 288 GB of HBM4 with 22 TB/s of bandwidth, and AMD's Instinct MI455X uses 432 GB of HBM4 with 23.3 TB/s.