What Is CoWoS? CoWoS-S vs CoWoS-R vs CoWoS-L Explained

CoWoS, short for Chip on Wafer on Substrate, is TSMC's 2.5D packaging technology. It places processor dies and high-bandwidth memory (HBM) stacks side by side on an interposer, then mounts that assembly on a package substrate. TSMC calls it the essential foundation for high-performance computing and AI products. The reason is physical: HBM needs thousands of short, dense connections that an ordinary package or circuit board cannot provide.

TSMC sells three variants that differ in the interposer: CoWoS-S uses a silicon interposer, CoWoS-R an organic redistribution-layer (RDL) interposer, and CoWoS-L an RDL interposer with small embedded silicon bridges. Figures below come from TSMC's own pages, as of October 2026.

What the name means

Chip on Wafer: the logic dies and memory stacks are bonded onto an interposer while it is still part of a wafer.
on Substrate: the finished interposer is attached to a conventional package substrate, which connects to the circuit board.

The "2.5D" label means the chips sit next to each other on a shared base rather than on top of one another. Stacking dies face to face in true 3D is a separate TSMC technology, SoIC, covered further down.

Why AI chips need an interposer

An HBM3E stack has a 1,024-bit interface and an HBM4 stack a 2,048-bit one (JEDEC). A GPU with 12 HBM4 stacks, such as AMD's Instinct MI455X, therefore needs more than 24,000 data lines to memory alone. An interposer carries wiring far finer than a package substrate, so memory can sit right next to the compute die.

Size is the second reason. A lithography scanner exposes a field of 26 mm by 33 mm, about 858 mm², and no single die can be larger than that "reticle limit" (overview). Putting several dies on an interposer measured in multiples of the reticle is how designers build packages that behave like one much larger chip.

CoWoS-S: the silicon interposer

CoWoS-S is the original version and has been in production since 2012. It uses one large silicon interposer with high-density wiring and embedded deep trench capacitors (eDTC), which support stable power delivery to the dies above. TSMC's CoWoS page says the interposer can reach 3.3 times the reticle size, about 2,700 mm²; for anything larger, TSMC recommends CoWoS-L or CoWoS-R.

CoWoS-R: the RDL interposer

CoWoS-R replaces silicon with a redistribution-layer interposer made of polymer and copper traces, with a minimum 4 µm pitch, meaning 2 µm line width and spacing. It has been in volume production since 2023. Because the RDL interposer is relatively flexible, it absorbs part of the thermal-expansion mismatch between the chip and the substrate, which TSMC says improves the integrity of the C4 bump joints.

CoWoS-L: RDL plus local silicon bridges

CoWoS-L combines an RDL-based interposer with local silicon interconnect (LSI) chips: small pieces of silicon embedded where dies need very dense die-to-die wiring, for example between two compute dies or between a compute die and an HBM stack. The LSI chips use multiple layers of sub-micron copper lines, and the package can also embed stand-alone eDTCs underneath the main die to improve power management.

TSMC's first CoWoS-L, at 3.5 times the reticle size, has been in volume production since 2024. This is the variant TSMC is scaling to larger packages. AMD, for example, says its Instinct MI455X joins its chiplets and 12 HBM4 stacks on an advanced CoWoS-L package (AMD).

CoWoS-S vs CoWoS-R vs CoWoS-L

Interposer material: silicon for S; polymer and copper RDL for R; RDL with embedded silicon bridges for L.
In volume production since: 2012 for S; 2023 for R; 2024 for L, at 3.5 reticles.
Size: S tops out at 3.3 reticles (about 2,700 mm²); TSMC points customers who need more area to R or L.
Where the finest wiring is: across the whole silicon interposer for S; in RDL layers with 2 µm line and space for R; in the LSI bridges for L.

How large CoWoS is getting

At its North America Technology Symposium in April 2026, TSMC said it was producing 5.5-reticle CoWoS and set out this plan (TSMC):

a 14-reticle CoWoS in 2028, able to integrate about 10 large compute dies and 20 HBM stacks;
versions beyond 14 reticles in 2029;
SoW-X, a 40-reticle system-on-wafer technology, also expected in 2029.

A year earlier TSMC had targeted 9.5-reticle CoWoS for 2027, with 12 or more HBM stacks per package, and had scheduled SoW-X for 2027 (TSMC, April 2025). Roadmaps move, so treat these dates as company targets rather than shipping dates.

CoWoS vs InFO vs SoIC

CoWoS is one part of TSMC's 3DFabric family:

InFO (Integrated Fan-Out) is wafer-level packaging built on a high-density RDL and through-InFO vias. Its InFO-PoP version stacks a mobile processor with DRAM and has no organic substrate or C4 bumps, which makes it thinner than flip-chip package-on-package (TSMC InFO).
SoIC is TSMC's 3D chip-stacking platform, with bond pitches starting below 10 µm; TSMC says its 3 nm chip stacking entered volume production in 2025. SoIC stacks can then be packaged with CoWoS or InFO (TSMC SoIC).
CoWoS is the 2.5D option for the largest HPC and AI packages with HBM.

CoWoS vs EMIB

Intel's closest equivalent is EMIB (Embedded Multi-die Interconnect Bridge), which uses small silicon bridges to connect neighbouring dies instead of a full-size interposer (overview). The idea resembles the LSI bridges in CoWoS-L; the main difference is that EMIB embeds its bridges in the package substrate, while CoWoS-L places them in an RDL interposer that sits on the substrate.

Why CoWoS capacity matters

According to TSMC, demand for CoWoS climbed further once generative AI took off in late 2022, and the company keeps adding advanced-packaging capacity. Because every HBM-based accelerator needs this kind of package, packaging capacity sits alongside wafer output as a factor in how many AI chips can be built. Our Chips section follows these announcements, and the companies buying the capacity are covered under Big Tech.

Frequently asked questions

What does CoWoS stand for?

CoWoS stands for Chip on Wafer on Substrate. It is TSMC's 2.5D packaging technology that places logic dies and HBM stacks side by side on an interposer.

What is the difference between CoWoS-S and CoWoS-L?

CoWoS-S uses a single silicon interposer of up to 3.3 reticles. CoWoS-L uses an RDL interposer with embedded silicon bridges, entered volume production at 3.5 reticles in 2024 and is the variant TSMC is scaling to larger packages.

Is CoWoS 2.5D or 3D packaging?

CoWoS is 2.5D: the chips sit next to each other on an interposer. TSMC's 3D stacking technology is SoIC, and SoIC stacks can be placed inside a CoWoS package.

What is the difference between CoWoS and EMIB?

Both connect dies through silicon. CoWoS uses an interposer under the chips, while Intel's EMIB embeds small silicon bridges directly in the package substrate.

How big can a CoWoS package be?

TSMC said in April 2026 that it produces 5.5-reticle CoWoS and plans a 14-reticle version, with about 10 compute dies and 20 HBM stacks, for 2028.