AMD's Linux drivers hint at GDDR7 memory in next-generation RDNA 5 GPUs

AMD is laying groundwork for its next-generation standalone graphics processors by integrating GDDR7 memory support into its open-source Linux kernel driver, according to reporting by Phoronix. The addition of new graphics IP blocks alongside this memory support indicates that software enablement for the company's upcoming discrete GPUs is progressing, though AMD has not formally identified the target architecture.

The shift to GDDR7 represents a significant marker for the forthcoming generation. Current Radeon RX 9000-series processors built on the RDNA 4 architecture rely on GDDR6 memory, making the driver support for GDDR7 one of the clearest signals yet that AMD is preparing its next-generation discrete Radeon graphics cards based on the RDNA 5 architecture.

Beyond memory support, AMD has submitted patches enabling IH 8.0, a new iteration of its Interrupt Handler IP block, and NBIF 7.10, the latest version of its New Bus Interface. Additional smaller patches prepare the driver for the new hardware. These submissions build on earlier driver work that introduced Display Core Next 6 (DCN6) and GFX 13.0.x support, demonstrating that AMD is methodically upstreaming support for multiple GPU components. However, while these changes clearly point to new graphics hardware, only the GDDR7 addition specifically suggests new discrete GPUs rather than other GPU types.

Chiplet designs and architecture flexibility

In August 2025, Laks Pappu, Senior Fellow at AMD, was identified as the lead architect for AMD's next-generation datacenter GPU and discrete graphics platforms. Before his LinkedIn profile was edited to remove the information, it indicated that Pappu was developing next-generation "competitive 2.5D/3.5D Chiplet-based and monolithic Graphics SoCs on various packaging technologies."

This disclosure suggested that AMD's upcoming GPU architecture could support multiple physical implementations—both multi-chiplet and monolithic designs—tailored to performance targets, cost considerations, market demands, and AMD's competitive positioning in different segments.

AMD has already demonstrated multi-chiplet GPU design with its Navi 31 processor, which concentrated graphics processing on a large Graphics Compute Die (GCD) while separating memory interfaces and caches into smaller Memory Cache Dies (MCDs). A more sophisticated approach could distribute graphics processing capabilities across multiple dies, though Pappu's profile did not reveal AMD's specific partitioning strategy for future GPUs.

Distributing compute resources across multiple dies would introduce substantially greater complexity than the current memory and cache separation model. Such designs would demand high-bandwidth, low-latency interconnects between dies, along with synchronization and coherency mechanisms, while software would ideally treat the chiplet collection as a single graphics processor.

Timeline and development status

Applying conventional GPU development timelines of 2.5 to 3.5 years, RDNA 5 may have already reached tape-out or entered early post-tape-out phases when the information became public in August 2025. This suggests AMD is likely conducting internal testing of the new GPUs at this stage.

AMD has not officially announced any details regarding RDNA 5 specifications or a launch timeline, so these driver developments should be interpreted cautiously. What remains certain is that AMD is developing standalone RDNA 5-based GPUs expected to use GDDR7 in at least some configurations, provided that ongoing supply constraints on high-bandwidth memory do not further restrict availability for consumer applications.