Former Microsoft Engineer Builds Custom RAM for Vintage PDP-11 With AI Assistance

Dave Plummer, who engineered Windows Task Manager, Windows Pinball, and TMOG during his time at Microsoft, has taken on an unconventional challenge: building RAM from the ground up for a vintage PDP-11 computer. The sticker shock of acquiring memory modules for the 1970-era machine prompted him to design his own circuit board rather than pay the going rate.

The PDP-11 platform could accommodate up to four megabytes of memory in its later iterations. To tackle the design work, Plummer turned to ChatGPT for guidance and leveraged EasyEDA, an online tool for circuit simulation. Despite acknowledging his inexperience with projects of this complexity, he proceeded to engineer a standalone RAM card compatible with the Q-Bus architecture that the PDP-11 employed for its core components. His prototype was then validated by connecting it to a backplane alongside an M8190 CPU board.

The finished circuit incorporated a Lattice MachXO2 FPGA (model 2000HC) functioning as the memory controller, paired with four ISSI memory chips rated at 1 MB each. Additional components included a U2S I/O chip, a set of DIP switches, communication ports, and various capacitors. The underlying M8190 board architecture features a 22-bit address bus, with the uppermost 256 KB reserved for input/output and read-only memory functions.

The project did not proceed without setbacks. Plummer had never flash-programmed an FPGA before, requiring multiple attempts to get the chip properly configured. A more fundamental challenge emerged when he encountered a quirk of the PDP-11's memory architecture: the system can only retrieve complete words—two bytes at a time—and designates the lowest address bit as a selector that determines whether the CPU accesses the low or high byte within that word.

This design constraint created complications for Plummer's memory controller. During read operations, the CPU extracts the correct byte, but the controller must still deliver a full word. On write operations, the controller must interpret the bit selector and ensure only the intended byte gets updated, since the bus carries an entire word that could otherwise corrupt data if written indiscriminately.

Plummer had not anticipated this architectural detail beforehand. An online commenter humorously observed that he had "built 4MB of memory that turned out to be 2MB," and Plummer acknowledged the memory "only returns every second word," confirming the pattern. Though no subsequent updates have surfaced, the issue appears to have been resolved through FPGA code modifications after other commenters highlighted the problem.

One suggestion involved bypassing the hardware approach entirely by implementing memory through software on a Raspberry Pi, connected directly to the PDP bus. Plummer responded that he had essentially completed that approach the previous week using a modern QBone DEC interface board, which itself houses a Beaglebone Black processor—functionally comparable to a Raspberry Pi.