AMD Prepares Linux Support for Three-Tier Core Architecture in Future Processors
AMD has submitted kernel patches revealing plans for a third core type—low-power cores designed for background tasks—signaling a shift toward heterogeneous processor designs similar to Intel's recent strategy.
Three-tier core design takes shape
The chipmaker has filed Linux kernel patches that add support for a new category of low-power CPU cores intended for its forthcoming heterogeneous processors, according to Phoronix. The updated patch distinguishes among three distinct core varieties: high-performance cores, efficiency cores, and low-power cores, indicating that AMD's next-generation platforms will incorporate all three types, with the low-power variant handling lightweight workloads.
AMD's heterogeneous architecture relies on CPUID Function 0x80000026 (Extended CPU Topology) to identify CPU types, with EBX bits [31:28] serving as the core classification mechanism. Previously, AMD categorized cores only as Performance and Efficiency variants. The latest patch introduces Low-Power cores to this taxonomy, allowing Linux to properly recognize and manage all three categories while ensuring AMD's power management systems work correctly with the new classification.
According to AMD engineer Vishal Badole, these cores are designed specifically for background and idle tasks where reducing energy consumption is more important than offering high performance.
Following Intel's heterogeneous path
Both AMD and Intel have pursued heterogeneous processor designs in recent years, combining performance-focused and energy-efficient core types to balance computational capability with power efficiency. Intel's latest CPU generations feature low-power cores positioned on the SoC tile to handle lighter workloads and extend laptop battery endurance. AMD appears to be adopting a comparable strategy, though the two companies differ in their technical approach: AMD maintains the same underlying architecture across core types with density and clock optimizations, whereas Intel employs entirely separate microarchitectures for each core class.
Limited details on implementation
Beyond the kernel patch specifics, AMD has disclosed minimal information regarding these low-power cores. The company characterized them as optimized for minimal power draw during background processing and idle states but declined to specify architectural differences from today's dense Zen 5c cores. The kernel patches themselves introduce no novel scheduling mechanisms or optimization routines beyond identifying the additional core category.
AMD has not indicated whether these cores will be based on Zen 5, Zen 6, or another future microarchitecture. Historically, AMD has favored deploying a single microarchitecture across one processor line, applying different optimizations for die layout and clock speeds rather than fundamentally different designs. This strategy streamlines software development and power management but typically results in higher power consumption than a purpose-built simplified microarchitecture would deliver.
Source: Tom's Hardware